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LH75400/01/10/11 (Preliminary) User's Guide
Table 19-6 and Table 19-7 describe the RSR/ECR Register for read operations.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:4
3
2
1
0
Table 19-6. RSR/ECR Register (Read Operations)
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
0
0
0
0
R
R
R
R
Table 19-7. RSR/ECR Register Definitions (Read Operations)
NAME
///
Reserved Do not modify. Read as zero.
Data Overrun Error
1 = Data is received and the FIFO is already full.
OVERRUN
This bit is cleared to 0 by a write to ECR. The FIFO contents remain valid
ERROR
since no further data is written when the FIFO is full, only the contents of the
shift register are overwritten. The CPU must now read the data in order to
empty the FIFO.
Break Error
1 = A break condition was detected, indicating that the received data input
was held LOW for longer than a full-word transmission time (defined as
start, data, parity, and stop bits).
BREAK
ERROR
This bit is cleared to 0 after a write to ECR. In FIFO Mode, this error is asso-
ciated with the character at the top of the FIFO. When a break occurs, only
one 0 character is loaded into the FIFO. The next character is only enabled
after the receive data input goes to a 1 (marking state) and the next valid start
bit is received.
Parity Error
PARITY
1 = The parity of the received data character does not match the parity
ERROR
selected as defined by bits [2] and [7] of the LCR_H Register (see
Section 19.3.1.7). This bit is cleared to 0 by a write to ECR.
Framing Error
FRAMING
1 = The received character did not have a valid stop bit (a valid stop bit is 1).
ERROR
This bit is cleared to 0 by a write to ECR.
27
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
11
10
9
8
7
///
0
0
0
0
0
R
R
R
R
R
UART0: 0xFFFC0000 + 0x004
UART1: 0xFFFC1000 + 0x004
DESCRIPTION
7/15/03
UART0 and UART1
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
0
0
0
0
0
R
R
R
R
R
17
16
0
0
R
R
1
0
0
0
R
R
19-9
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