Ssp Clock Prescaler Register; Table 9-27. Sspprescaler Register; Table 9-28. Sspprescaler Register Definitions; Table 9-29. Sspprescaler Register Values - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

9.3.2.12 SSP Clock Prescaler Register

SSPPrescaler is the SSP Clock Prescaler Register. The active bits used in this register are
Read/Write.
This register divides down the SSP clock frequencies using the appropriate formula:
• If SSPPrescaler > 0:
• If SSPPrescaler = 0:
Table 9-29 shows the valid values for SSPPrescaler and the resulting internal clock
frequency. All other SSPPrescaler values are invalid.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
ƒ(SSP) = ƒ(HCLK) ÷ (2 * SSPPrescaler)
ƒ(SSP) = ƒ(HCLK)

Table 9-27. SSPPrescaler Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
—
0 0 0 0 0
R R R R R

Table 9-28. SSPPrescaler Register Definitions

FIELD NAME
Reserved Writing to these bits has no effect. Reading returns 0.
///
SSP Clock Frequencies Divides down the SSP clock frequencies
SSPPRESCALER
(see Table 9-29).

Table 9-29. SSPPrescaler Register Values

SSPPrescaler
00000000 (default)
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
Reset, Clock, and Power Controller
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
0 0 0 0 0
R R R RW RW
0xFFFE2000 + 0x44
DESCRIPTION
DIVIDER
VALUE
1
2
4
8
16 ƒ(HCLK)/16
32 ƒ(HCLK)/32
64 ƒ(HCLK)/64
128 ƒ(HCLK)/128
256 ƒ(HCLK)/256
7/15/03
21 20 19 18
0 0 0 0
R R R R
5 4 3 2
SSPPRESCALER
0 0 0 0
RW RW RW RW
ƒ(SSP)
ƒ(HCLK)
ƒ(HCLK)/2
ƒ(HCLK)/4
ƒ(HCLK)/8
17 16
0 0
R R
1 0
0 0
RW RW
9-17