Sharp Blue Treak LH75400 User Manual page 7

LH75400/01/10/11 (Preliminary) User's Guide
13.4 HR-TFT Controller...................................................................................... 13-24
13.5 Timing Waveforms ..................................................................................... 13-30
Chapter 14 - Liquid Crystal Display Controller
14.1 LCDC Features ............................................................................................ 14-3
14.2 LCDC Theory of Operation........................................................................... 14-3
14.3 LCDC Programmer's Model ......................................................................... 14-7
13.3.2.1 Horizontal Timing Panel Control Register .................................... 13-11
13.3.2.2 Horizontal Timing Restrictions...................................................... 13-12
13.3.2.3 Vertical Timing Panel Control Register......................................... 13-13
13.3.2.4 Clock and Signal Polarity Control Register................................... 13-14
13.3.2.5 Upper Panel Frame Buffer Base Address Register...................... 13-15
13.3.2.6 Lower Panel Frame Buffer Base Address Register...................... 13-16
13.3.2.7 Interrupt Enable Register.............................................................. 13-17
13.3.2.8 LCD Panel Parameters, LCD Panel Power, and
CLCDC Control Register ........................................................................ 13-18
13.3.2.9 Raw Interrupt Status Register ...................................................... 13-20
13.3.2.10 Final Masked Interrupts Register................................................ 13-21
13.3.2.11 LCD Upper Panel Frame Buffer Current Address Register........ 13-22
13.3.2.12 256 × 16-bit Color Palette Register ............................................ 13-23
13.3.3 CLCDC Interrupts ................................................................................ 13-24
13.4.1 HRTFTC Operating Modes ................................................................. 13-24
13.4.1.1 Bypass Mode................................................................................ 13-24
13.4.1.2 HR-TFT Mode............................................................................... 13-24
13.4.2 HRTFTC Theory of Operation ............................................................. 13-25
13.4.3 HRTFTC Programmer's Model............................................................ 13-25
13.4.4 HRTFTC Register Summary ............................................................... 13-25
13.4.5 HRTFTC Register Definitions .............................................................. 13-26
13.4.5.1 Setup Register.............................................................................. 13-26
13.4.5.2 Control Register............................................................................ 13-27
13.4.5.3 Timing1 Register .......................................................................... 13-28
13.4.5.4 Timing2 Register .......................................................................... 13-29
13.5.1 STN Horizontal Timing ........................................................................ 13-30
13.5.2 STN Vertical Timing ............................................................................ 13-30
13.5.3 TFT Horizontal Timing ......................................................................... 13-30
13.5.4 TFT Vertical Timing ............................................................................. 13-30
13.5.5 HR-TFT Horizontal Timing Waveforms ............................................... 13-30
13.5.6 HR-TFT Vertical Timing Waveforms.................................................... 13-30
14.2.1 LCD DMA FIFOs ................................................................................... 14-4
14.2.2 Pixel Serializer....................................................................................... 14-4
14.2.3 How Pixels are Stored in Memory ......................................................... 14-4
14.2.4 Palette RAM .......................................................................................... 14-5
14.2.5 Grayscale Algorithm .............................................................................. 14-5
14.2.6 Supported Grayscale............................................................................. 14-6
14.3.1 LCDC Register Summary ...................................................................... 14-7
14.3.2 LCDC Register Definitions .................................................................... 14-8
14.3.2.1 Horizontal Timing Panel Control Register ...................................... 14-8
14.3.2.2 Horizontal Timing Restrictions........................................................ 14-9
6/17/03
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