Lcd Clock Prescaler Register; Table 9-24. Lcdprescaler Register; Table 9-25. Lcdprescaler Register Definitions; Table 9-26. Lcdprescaler Register Values - Sharp Blue Treak LH75400 User Manual

Reset, Clock, and Power Controller

9.3.2.11 LCD Clock Prescaler Register

LCDPrescaler is the LCD Clock Prescaler Register. The active bits used in this register
are Read/Write.
This register divides down the LCD clock frequencies using the appropriate formula:
• If LCDPrescaler > 0:
• If LCDPrescaler = 0:
Table 9-26 shows the valid values for LCDPrescaler and the resulting internal clock
frequency. All other LCDPrescaler values are invalid.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
9-16
ƒ(LCD) = ƒ(HCLK) ÷ (2 * LCDPrescaler)
ƒ(LCD) = ƒ(HCLK)

Table 9-24. LCDPrescaler Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 9-25. LCDPrescaler Register Definitions

FIELD NAME
Reserved Writing to these bits has no effect. Reading returns 0.
///
LCD Clock Frequencies Divides down the LCD clock frequencies
LCDPRESCALER
(see Table 9-26).

Table 9-26. LCDPrescaler Register Values

LCDPRESCALER
00000000 (default)
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
0 0 0 0
R R R RW RW
0xFFFE2000 + 0x40
DESCRIPTION
DIVIDER
VALUE
1
2
4
8
ƒ(HCLK)/16
16
ƒ(HCLK)/32
32
ƒ(HCLK)/64
64
ƒ(HCLK)/128
128
ƒ(HCLK)/256
256
7/15/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
LCDPRESCALER
0 0 0 0 0
RW RW RW RW
ƒ(LCD)
ƒ(HCLK)
ƒ(HCLK)/2
ƒ(HCLK)/4
ƒ(HCLK)/8
17 16
0 0
R R
1 0
0 0
RW RW