Uart0 And Uart1 Programmer's Model; Uart0 And Uart1 Register Summary; Table 19-1. Uart0 And Uart1 Register Summary - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

19.3 UART0 and UART1 Programmer's Model

While UART0 and UART1 offer similar internal functionality to the industry standard
16C550, the programmer's interface differs. That information is covered here.
The base address for UART0 is:
UART0 Base Address: 0xFFFC0000
The base address for UART1 is:
UART1 Base Address: 0xFFFC1000
The following locations are reserved and must not be used during normal operation:
• 0xFFFC0008 through 0xFFFC0014
• 0xFFFC001C through 0xFFFC0020
• 0xFFFC004C through 0xFFFC007C
• 0xFFFC0080 through 0xFFFC008C
• 0xFFFC0090 through 0xFFFC0FFC

19.3.0.1 UART0 and UART1 Register Summary

NAME
DR
RSR/ECR
///
FR
///
IBRD
FBRD
LCTRL_H
CTRL
IFLS
IMSC
RIS
MIS
ICR
DMACTRL
///
///
///

Table 19-1. UART0 and UART1 Register Summary

ADDRESS
TYPE
OFFSET
0x000 RW
0x004 RW
0x008 - 0x014
0x018 R
0x01C - 0x020
0x024 R
0x028
RW
0x02C RW
0x030
RW
0x034 RW
0x038
RW
0x03C R
0x040 R
0x044 W
0x048 RW
0x04C - 0x07C
0x080 - 0x08C
0x090 - 0xFFC
7/15/03
RESET
VALUE
Data read or written from the interface. It is
0x---
12 bits wide on a read and 8 on a write.
Receive Status Register (read)/Error Clear
0x0
Register (write)
Reserved
0x00000090 Flag Register (read only)
Reserved
0x0000 Integer Baud Rate Divisor Register
0x00 Fractional Baud Rate Divisor Register
0x00 Line Control Register, HIGH byte
0x0300 UART Control Register
0x12 Interrupt FIFO Level Select Register
0x000 Interrupt Mask Set/Clear Register
0x00- Raw Interrupt Status Register
0x00- Masked Interrupt Status Register
Interrupt Clear Register
0x00 DMA Control Register
Reserved
Reserved
Reserved
UART0 and UART1
DESCRIPTION
19-5