Interrupt Clear Register; Table 12-10. Clr Register; Table 12-11. Clr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

12.3.2.9 Interrupt Clear Register

The Interrupt Clear Register clears the status flags. The active bits used in this register are
Write Only. This register has no default value after Reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 12-11. CLR Register Definitions

BIT NAME
31:8 /// Reserved Do not write.
Clear/Do Not Clear ErrorInt3 Flag
7 ClearE3 0 = Does not clear the ErrorInt3 flag in the Status Register.
1 = Clears the ErrorInt3 flag in the Status Register.
Clear/Do Not Clear ErrorInt2 Flag
6 ClearE2 0 = Does not clear the ErrorInt2 flag in the Status Register.
1 = Clears the ErrorInt2 flag in the Status Register.
Clear/Do Not Clear ErrorInt1 Flag
5 ClearE1 0 = Does not clear the ErrorInt1 flag in the Status Register.
1 = Clears the ErrorInt1 flag in the Status Register.
Clear/Do Not Clear ErrorInt0 Flag
4 ClearE0 0 = Does not clear the ErrorInt0 flag in the Status Register.
1 = Clears the ErrorInt0 flag in the Status Register.
Clear/Do Not Clear Int3 Flag
3 Clear3 0 = Does not clear the Int3 flag in the Status Register.
1 = Clears the Int3 flag in the Status Register.
Clear/Do Not Clear Int2 Flag
2 Clear2 0 = Does not clear the Int2 flag in the Status Register.
1 = Clears the Int2 flag in the Status Register.
Clear/Do Not Clear Int1 Flag
1 Clear1 0 = Does not clear the Int1 flag in the Status Register.
1 = Clears the Int1 flag in the Status Register.
Clear/Do Not Clear Int0 Flag
0 Clear0 0 = Does not clear the Int0 flag in the Status Register.
1 = Clears the Int0 flag in the Status Register.

Table 12-10. CLR Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
0 0 0 0
R R R W
0xFFFE1000 + 0x0F4
FUNCTION
7/15/03
Direct Memory Access Controller
22 21 20 19 18
0 0 0 0
R R R R
6 5 4 3
0 0 0 0
W W W W W
17 16
0 0 0
R R R
2 1 0
0 0 0
W W
12-13