Real-Time Clock
17.3.2.6 Read/Write Load Register 0
LR0 is the Lower 16-bit Read/Write Load Register. Writes to this register load the least-
significant 16 bits of an Intermediate Register. The intermediate Register is not loaded into
the free-running counter until the rising edge of a 1 Hz clock follows a write operation to
LR1. Read operations return the last value written.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BIT
31:16
15:0
17-8
31
30
29
28
27
—
—
—
—
—
R
R
R
R
R
15
14
13
12
11
—
—
—
—
—
RW
RW
RW
RW
RW
Table 19. LR0 Register Definitions
NAME
///
Reserved
RTCLR0 RTC Load Register 0 Specifies the lower 16-bit Counter Load Register.
LH75400/01/10/11 (Preliminary) User's Guide
Table 18. LR0 Register
26
25
24
23
///
—
—
—
—
R
R
R
R
10
9
8
7
RTCLR0
—
—
—
—
RW
RW
RW
RW
0xFFFE0000 + 0x14
FUNCTION
6/17/03
22
21
20
19
18
—
—
—
—
—
R
R
R
R
R
6
5
4
3
2
—
—
—
—
—
RW
RW
RW
RW
RW
17
16
—
—
R
R
1
0
—
—
RW
RW