Port D Data Direction Register; Table 21-17. Pdddr Register; Table 21-18. Pdddr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

21.2.3.8 Port D Data Direction Register

PDDDR is the Port D Data Direction Register. The active bits used in this register are
Read/Write.
Bits set in the PDDDR set the corresponding PD pin to be an output:
• Bit [6] controls pin 72 when the pin is configured as PD6. It does not control pin 72 when
the pin is configured as INT6 or DREQ.
• Bit [5] controls pin 73 when the pin is configured as PD5. It does not control pin 73 when
the pin is configured as INT5 or DACK.
• Bit [4] controls pin 74 when the pin is configured as PD4. It does not control pin 74 when
the pin is configured as INT4 or UARTRX1.
• Bit [3] controls pin 76 when the pin is configured as PD3. It does not control pin 76 when
the pin is configured as INT3 or UARTTX1.
• Bit [2] controls pin 77 when the pin is configured as PD2. It does not control pin 77 when
the pin is configured as INT2.
• Bit [1] controls pin 78 when the pin is configured as PD1. It does not control pin 78 when
the pin is configured as INT1.
• Bit [0] controls pin 79 when the pin is configured as PD0. It does not control pin 79 when
the pin is configured as INT0.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6:0

Table 21-17. PDDDR Register

31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
0 0 0 0
R R R R

Table 21-18. PDDDR Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Port D Output/Input
Port D Data Direction
Bits set = Port D output.
Bits cleared = Port D input.
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0 0
R R R R R
0xFFFDE000 + 0x0C
6/17/03
General Purpose Input/Output
22 21 20 19
0 0 0 0
R R R R
6 5 4 3
Port D Data Direction
0 0 0 0
RW RW RW RW RW
FUNCTION
18 17 16
0 0 0
R R R
2 1 0
0 0 0
RW RW
21-11