Interrupt Enable Register; Table 13-20. Intrenable Register; Table 13-21. Intrenable Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

13.3.2.7 Interrupt Enable Register

INTRENABLE is the Interrupt Enable Register. Setting bits within this register enables the
corresponding raw interrupt Status bit values to be passed to the Raw Interrupt Status
Register (see Chapter 13). The active bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:5
4
3
2
1
0

Table 13-20. INTRENABLE Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 13-21. INTRENABLE Register Definitions

NAME
Reserved Writing to these bits has no effect. Reading returns 0.
///
AHB Master Error Interrupt Enable
MBERRINTRENB
1 = Enables the AHB Master Error Interrupt to be passed to the
Vertical Compare Interrupt Enable
VCOMPINTRENB
1 = Enables the Vector Compare Interrupt to be passed to the Raw
Next Base Update Interrupt Enable
LNBUINTRENB
1 = Enables the Next Base Update Interrupt to be passed to the
FIFO Underflow Interrupt Enable
FUFINTRENB
1 = Enables the FIFO Underflow Interrupt to be passed to the Raw
/// Reserved Writing to this bit has no effect. Reading returns 0.
Color Liquid Crystal Display Controller
26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0
R R R R
0xFFFF4000 + 0x18
DESCRIPTION
Raw Interrupt Status Register.
Interrupt Status Register.
Raw Interrupt Status Register.
Interrupt Status Register.
7/15/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
R R RW RW RW
17 16
0 0
R R
1 0
///
0 0
RW R
13-17