Brgb Divisor Least Significant Byte Register; Table 20-67. Bbl Register; Table 20-68. Bbl Register Definitions - Sharp Blue Treak LH75400 User Manual

UART2

20.3.2.29 BRGB Divisor Least Significant Byte Register

Register Bank: 3
BBL is the BRGB Divisor Least Significant Byte Register. The BBL Register contains the
least-significant byte of the BRGB divisor/count value. Acceptable values for this register
range from 2 to 65,535. The DLAB bit in the LCR Register must be set to access this reg-
ister (see Chapter 19, Section 19.3.1.9).
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
20-40

Table 20-67. BBL Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 20-68. BBL Register Definitions

NAME
/// Reserved Do not modify. Read as zero.
Least-Significant Byte of the BRGB Divisor/Count Value Bit [7]
D7:D0
holds the most-significant bit. Bit [0] holds the least-significant bit.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
D7 D6
0 0 0 0
R R R RW RW
0xFFFC2000 + 0x00
DESCRIPTION
6/17/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
D5 D4 D3 D2
0 0 0 0 1
RW RW RW RW
17 16
0 0
R R
1 0
D1 D0
0 1
RW RW