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Glossary
Byte Lane
A data path that is one byte wide.
CAN
Controller Area Network. A serial bus protocol specifically designed for electrically noisy
environments. For more information, see www.can.bosch.com
Chip
A functional element made by dividing a portion of semiconductor wafer material, some-
times referred to as a 'die' or plural, 'dice'.
CLCDC
The on-chip Color Liquid Crystal Display Controller.
Core
See ARM7TDMI-S Core.
CPSR
Current Program Status Register. In ARM architecture, the CPSR is the register that stores
the condition code bits.
CSTN
Color Super-Twist Nematic. A type of color Liquid Crystal Display that uses transmitted
light to form a display.
Embedded SRAM
Static Random Access Memory that is present in the processor for application use. The
LH75400/01/10/11 has 32KB of embedded SRAM (eSRAM).
Endianness
Describes the bit, byte, or word sequence of data communication or storage, associating
the most significant or least significant end of a data sequence with the lowest address or
with the beginning of reception or transmission. See Big-endian and Little-endian.
FIQ
Fast Interrupt Request. For more information, refer to ARM Architecture Manual at the
ARM Ltd. website: www.arm.com.
GPIO
General Purpose Input and Output
Half-Word
In the context of 32-bit SoCs, a half-word is an ordered pair of bytes totaling 16-bits. Half-words
are always shown with the MSB at the left and the LSB on the right.
27-2
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
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