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LH75400/01/10/11 (Preliminary) User's Guide
14.1 LCDC Features
The LCDC supports:
• Supported Monochrome STN Panels
– Single-panel monochrome STN panels (4-bit and 8-bit bus interfaces)
– Dual-panel monochrome STN panels (4-bit bus interface per panel)
• Supported Resolutions
– Up to 640 × 480 DPI
• Supported Data Format
– Little Endian
• Additional Features
– Programmable timing for different display panels
– 256-entry, 16-bit palette RAM physically arranged as a 128 × 32-bit RAM
– AC bias signal for STN panels
• Programmable Parameters
– Horizontal
– Horizontal Front Porch (HFP)
– Horizontal Back Porch (HBP)
– Horizontal Synchronization Pulse Width (HSW)
– Number of Pixels per Line (PPL)
– Vertical
– Vertical Front Porch (VFP)
– Vertical Back Porch (VBP)
– Vertical Synchronization Pulse Width (VSW)
– Number of Lines per Panel (LPP)
– Panel-related Parameters
– Display type: STN mono
– Bits-per-pixel
– STN 4-bit Interface Mode
– STN Single Panel Mode
– AC panel bias
– Panel clock frequency
– Number of panel clocks per line
– Signal polarity, active HIGH or LOW
– Little Endian data format
– Interrupt-generation event
14.2 LCDC Theory of Operation
The LCDC fetches data from Static Memory. The AHB master interface, which is con-
nected directly to the AHB system bus, transfers display data from the memory to the LCD
DMA FIFOs. The AHB master interface loads the upper panel base address into the AHB
address incrementer when a new frame is recognized. It monitors both the upper and
lower LCD DMA FIFO levels, and asserts HBUSREQM to request display data from
memory, filling them to a level above the programmed watermark.
Liquid Crystal Display Controller
6/17/03
14-3
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