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LH75400/01/10/11 (Preliminary) User's Guide
BIT
31:12
11
10
9
8
7:0
Table 19-3. DR Register Definitions
NAME
///
Reserved Do not modify. Read as zero.
Receive FIFO Full/Empty
OVERRUN
0 = There is an empty space in the FIFO and a new character can be written
ERROR
to it.
1 = Data is received and the receive FIFO is already full.
Break Error
1 = A break condition was detected, indicating that the received data input
was held LOW for longer than a full-word transmission time (defined as
start, data, parity and stop bits).
BREAK
ERROR
This bit is cleared to 0 after a write to ECR. In FIFO Mode, this error is as-
sociated with the character at the top of the FIFO. When a break occurs, only
one 0 character is loaded into the FIFO. The next character is only enabled
after the receive data input goes to a 1 (marking state) and the next valid
start bit is received.
Parity Error
1 = The parity of the received data character does not match the parity
PARITY
selected as defined by bits [2] and [7] of the LCR_H Register (see
ERROR
Section 19.3.1.9). In FIFO Mode, this error is associated with the char-
acter at the top of the FIFO.
Framing Error
1 = The received character did not have a valid stop bit (a valid stop bit
FRAMING
is 1). In FIFO Mode, this error is associated with the character at the top
ERROR
of the FIFO. Framing errors are not generated for the number of stop
bits; e.g.: when one is expected and two are recieved, or two are expect-
ed and one is recieved.
Receive/Transmit Data Character
DATA
Read = Receive data character.
Write = Transmit data character.
DESCRIPTION
7/15/03
UART0 and UART1
19-7
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