Table of Contents
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List of Tables
Preface
Table 1. Register Name .......................................................................................... xxxiii
Table 2. Bit Definitions ............................................................................................ xxxiii
Chapter 1 - Introduction
Table 1-1. Feature Summary ..................................................................................... 1-1
Table 1-2. Bus Master Priority.................................................................................... 1-2
Table 1-3. Device Operating Modes........................................................................... 1-3
Table 1-4. Linear Regulator Ramp-up Time............................................................... 1-5
Chapter 2 - LH75401 SoC
Table 2-1. LH75401 Numerical Pin List...................................................................... 2-5
Table 2-2. LH75401 Signal Descriptions.................................................................... 2-9
Chapter 3 - LH75411 SoC
Table 3-1. LH75411 Numerical Pin List...................................................................... 3-5
Table 3-2. LH75411 Signal Descriptions.................................................................... 3-9
Chapter 4 - LH75400 SoC
Table 4-1. LH75400 Numerical Pin List...................................................................... 4-5
Table 4-2. LH75400 Signal Descriptions.................................................................... 4-9
Chapter 5 - LH75410 SoC
Table 5-1. LH75410 Numerical Pin List...................................................................... 5-5
Table 5-2. LH75410 Signal Descriptions.................................................................... 5-9
Chapter 6 - Memory Interface Architecture
Table 6-1. Memory Mapping ...................................................................................... 6-2
Table 6-2. External Memory Section Mapping ........................................................... 6-3
Table 6-3. Primary AHB Peripheral Register Mapping............................................... 6-3
Table 6-4. APB Peripheral Register Mapping ............................................................ 6-4
Chapter 7 - Static Memory Controller
Table 7-1. Address Bus Organization ........................................................................ 7-1
Table 7-2. SMC Bus Turnaround Usage .................................................................... 7-8
Table 7-3. 8-bit External Bus Read ............................................................................ 7-9
Table 7-4. 16-bit External Bus Read .......................................................................... 7-9
Table 7-5. 8-bit External Bus Write .......................................................................... 7-10
Table 7-6. 16-bit External Bus Write ........................................................................ 7-10
Table 7-7. SMC Memory Bank Address Space........................................................ 7-12
Table 7-8. SMC Register Summary ......................................................................... 7-12
Table 7-9. BCR0 Register (16-bit Mode).................................................................. 7-13
Table 7-10. BCR0 Register (8-bit Mode).................................................................. 7-13
Table 7-11. BCR0 Register Definitions .................................................................... 7-14
Table 7-12. BCR1 Register ...................................................................................... 7-15
Table 7-13. BCR1 Register Definitions .................................................................... 7-15
Table 7-14. BCR2 Register ...................................................................................... 7-17
6/17/03
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