Interrupt Identification/Clear Register; Table 18-13. Iir/Icr Register (Read Characteristic); Table 18-14. Iir/Icr Register Definitions (Read Operation) - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

18.5.2.6 Interrupt Identification/Clear Register

IIR is the Interrupt Identification Register. The interrupt status is read from this register.
ICR is the Interrupt Clear Register. A write of any value to this register clears the SSP
receive FIFO Overrun Interrupt. This interrupt-clearing mechanism is in addition to the
other mechanism in the CTRL1 Register. Therefore, clearing the RORIE bit in the CTRL1
Register also clears the overrun condition if already asserted. All the bits clear to zero after
a System Reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 18-13. IIR/ICR Register (Read Characteristic)

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 18-14. IIR/ICR Register Definitions (Read Operation)

BITS NAME
31:16 /// Reserved Reading from these bits returns 0.
15:3 /// Reserved Unpredictable behavior when read.
Read SSP Receive FIFO Overrun Interrupt Status
2 RORIS
0 = SSPRORINTR is not asserted.
1 = SSPRORINTR is asserted.
Read SSP Transmit FIFO Service Request Interrupt Status
1 TIS
0 = SSPTXINTR is not asserted.
1 = SSPTXINTR is asserted.
Read SSP Receive FIFO Service Request Interrupt Status
0 RIS
0 = SSPRXINTR is not asserted.
1 = SSPRXINTR is asserted.
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
///
0 0 0 0 0
R R R R R
0xFFFC6000 + 0x014
DESCRIPTION
6/17/03
Synchronous Serial Port
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
TIS
0 0 0 0 0
R R R R R
16
0
R
0
RIS
0
R
18-17