Table 11-4. Ebi_Mux Register Definitions - Sharp Blue Treak LH75400 User Manual

I/O Configuration
11-4

Table 11-4. EBI_MUX Register Definitions

BITS NAME
31:15 /// Reserved Writing to these bits has no effect. Reading returns 0.
PA7/D15 to PA0/D8 Source
14 DATA
0 = PA7 to PA0
1 = D15 to D8
PB5/nWAIT Source
13 nWAIT
0 = PB5
1 = nWAIT
PB4/nBLE1 Source
12 nBLE1
0 = PB4
1 = nBLE1
PB3/nBLE0 Source
11 nBLE0
0 = PB3
1 = nBLE0
PB2/nCE3 Source
10 nCE3
0 = PB2
1 = nCE3
PB1/nCE2 Source
9 nCE2
0 = PB1
1 = nCE2
PB0/nCE1 Source
8 nCE1
0 = PB0
1 = nCE1
PC7/A23 Source
7 A23
0 = PC7
1 = A23
PC6/A22 Source
6 A22
0 = PC6
1 = A22
PC5/A21 Source
5 A21
0 = PC5
1 = A21
PC4/A20 Source
4 A20
0 = PC4
1 = A20
PC3/A19 Source
3 A19
0 = PC3
1 = A19
PC2/A18 Source
2 A18
0 = PC2
1 = A18
PC1/A17 Source
1 A17
0 = PC1
1 = A17
PC0/A16 Source
0 A16
0 = PC0
1 = A16
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
6/17/03