Vic Register Definitions; Irq Status Register; Table 10-3. Irqstatus Register; Table 10-4. Irqstatus Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide
VectCtrl 12
VectCtrl 13
VectCtrl 14
VectCtrl 15

10.2.2 VIC Register Definitions

10.2.2.1 IRQ Status Register

IRQStatus is the IRQ Status Register. This Read Only register provides the status of inter-
rupts [31:0] after IRQ masking.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:0 IRQStatus
Table 10-2. VIC Register Summary (Cont'd)
NAME ADDRESS OFFSET TYPE
0x230
0x234
0x238
0x23C
/// 0x300
/// 0x304
/// 0x308
/// 0x30C
/// 0x310

Table 10-3. IRQStatus Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 10-4. IRQStatus Register Definitions

NAME
Interrupt Status After Masking Shows the status of the interrupts after
masking by the IntEnable and IntSelect Registers.
0 = Interrupt is not active.
1 = Interrupt is active and generates an IRQ exception to the ARM7TDMI-S core.
Bits [31:0] correspond to the interrupt order in the Interrupt Assignments
Table (see Table 10-1).
RESET
VALUE
RW 0x00
RW 0x00
RW 0x00
RW 0x00
R 0x0
26 25 24 23 22
IRQStatus
0 0 0 0 0
R R R R R
10 9 8 7 6
IRQStatus
0 0 0 0 0
R R R R R
0x000
0xFFFFF000 +
DESCRIPTION
6/17/03
Vectored Interrupt Controller
DESCRIPTION
Vector Control 12 Register
Vector Control 13 Register
Vector Control 14 Register
Vector Control 15 Register
Reserved
Reserved
Reserved
Reserved
Reserved
21 20 19 18
0 0 0 0
R R R R
5 4 3 2
0 0 0 0
R R R R
17 16
0 0
R R
1 0
0 0
R R
10-9