Table 15-8. Inten0 Register; Table 15-9. Inten0 Register Definitions; Timer 0 Interrupt Control Register (Inten0) - Sharp LH79524 User Manual

Timers

15.2.2.3 Timer 0 Interrupt Control Register (INTEN0)

This register allows software to enable and disable individual interrupts as needed.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7
6
5
4
3
2
1
0
15-10

Table 15-8. INTEN0 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 15-9. INTEN0 Register Definitions

NAME
Reserved Reading this field returns 0. Write the reset value.
///
Timer 0 Interrupt Enable During Capture E Operation
CAPE_EN
1 = Interrupt enabled for capture E
0 = Interrupt disabled for capture E
Timer 0 Interrupt Enable During Capture D Operation
CAPD_EN
1 = Interrupt enabled for capture D
0 = Interrupt disabled for capture D
Timer 0 Interrupt Enable During Capture C Operation
CAPC_EN
1 = Interrupt enabled for capture C
0 = Interrupt disabled for capture C
Timer 0 Interrupt Enable During Capture B Operation
CAPB_EN
1 = Interrupt enabled for capture B
0 = Interrupt disabled for capture B
Timer 0 Interrupt Enable During Capture A Operation
CAPA_EN
1 = Interrupt enabled for capture A
0 = Interrupt disabled for capture A
Timer 0 Interrupt Enable Upon Compare 1
CMP1_EN
1 = Interrupt enabled for compare 1
0 = Interrupt disabled for compare 1
Timer 0 Interrupt Enable Upon Compare 0
CMP0_EN
1 = Interrupt enabled for compare 0
0 = Interrupt disabled for compare 0
Timer 0 Interrupt Overflow Enable
OVF_EN
1 = Interrupt enabled for counter overflows
0 = Interrupt disabled for counter overflows
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RO RW
0xFFFC4000 + 0x08
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW