Vector Control Registers; Table 10-25. Vectctrl Registers; Table 10-26. Vectctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

Vectored Interrupt Controller

10.2.2.12 Vector Control Registers

There are 16 Vector Control Registers, designated VectCtrl0 through VectCtrl15. These
registers select the interrupt source for the given vectored interrupt. The active bits used
in these registers are Read/Wrote.
Vectored interrupts are only generated if the interrupt is enabled. The specific interrupt is
enabled in the IntEnable Register (see Section 10.2.2.5), and the interrupt is set to generate
an IRQ interrupt in the IntSelect Register (Section 10.2.2.4). This prevents multiple interrupts
from being generated by a single request if the controller is programmed incorrectly.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:6
5
4:0
10-20

Table 10-25. VectCtrl Registers

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 10-26. VectCtrl Register Definitions

NAME
Reserved Do not modify. Read as zero.
///
Vector Interrupt Enable Enables the vector interrupt. This bit is cleared
E
on System Reset.
Interrupt Source Selection Selects the interrupt source from any of the
IntSource
32 interrupt sources.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0
R R R R
VectCtrl0: 0xFFFFF000 +
VectCtrl1: 0xFFFFF000 +
VectCtrl2: 0xFFFFF000 +
VectCtrl3: 0xFFFFF000 +
VectCtrl4: 0xFFFFF000 +
VectCtrl5: 0xFFFFF000 +
VectCtrl6: 0xFFFFF000 +
VectCtrl7: 0xFFFFF000 +
VectCtrl8: 0xFFFFF000 +
VectCtrl9: 0xFFFFF000 +
VectCtrl10: 0xFFFFF000 +
VectCtrl11: 0xFFFFF000 +
VectCtrl12: 0xFFFFF000 +
VectCtrl13: 0xFFFFF000 +
VectCtrl14: 0xFFFFF000 +
VectCtrl15: 0xFFFFF000 +
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
E IntSource
0 0 0 0 0
R RW RW RW RW
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
17 16
0 0
R R
1 0
0 0
RW RW