Lcdc Registers; Table 26-9. Lcdc Register Summary - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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Register Map

26.9 LCDC Registers

Base Address: 0xFFFF4000
NAME
Timing0
Timing1
Timing2
///
UPBASE
LPBASE
INTRENABLE
CTRL
Status
Interrupt
UPCURR
LPCURR
///
Palette
///
NOTE: These registers pertain to the LH75400 and LH75410 SoC devices only.
26-8

Table 26-9. LCDC Register Summary

ADDRESS
RESET
TYPE
OFFSET
VALUE
0x000
RW
0x00000000 Horizontal Timing Panel Control Register
0x004
RW
0x00000000 Vertical Timing Panel Control Register
0x008
RW
0x0000000 Clock and Signal Polarity Control Register
0x00C
RW
0x010
RW
0x0000000 Upper Panel Frame Buffer Base Address Register
0x014
RW
0x00000000 Lower Panel Frame Buffer Base Address Register
0x018
RW
0x00000000 Interrupt Enable Register
0x01C
RW
0x0000
0x020
RW
0x00000000 Raw Interrupt Status Register
0x024
R
0x00000000 Final Masked Interrupts Register
0x028
R
0x00000000 Upper Panel Frame Buffer Current Address Register
0x02C
R
0x00000000 Lower Panel Frame Buffer Current Address Register
0x030 - 0x1FC
0x00000
0x200 - 0x3FC
RW
0x400 - 0x7FF
6/17/03
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
Reserved
LCD Panel Parameters, LCD Panel Power, and
LCDC Control Register
Reserved
LCD Palette Register. Palette is addressed at 32 bits.
Reserved

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This manual is also suitable for:

Blue treak lh75401Blue treak lh75410Blue treak lh75411

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