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UART2
20.3.2.9 Line Status Register
Register Bank: 0
LSR is the Line Status Register. The LSR Register holds the status of the serial link. It is
provided for compatibility with the Intel 8250A UART. This register shares the following five
bits with the RST Register (described in Section 20.3.2.17):
• BkD
• FE
• PE
• OE
• RFIR.
When this register is read, the read operation clears bits [7:0] of the RST Register and bits
[4:0] of this register. Similarly, these same bits in the RST and LSR registers get cleared
when the RST Register is read.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:7
6
TxST
5
TFST
4
3
2
1
0
RFIR
20-20
31
30
29
28
27
0
0
0
0
R
R
R
R
15
14
13
12
11
///
0
0
0
0
R
R
R
R
Table 20-28. LSR Register Definitions
///
Reserved Do not modify. Read as zero.
Transmit Machine Status Bit This bit is functionally identical to the TxIR bit of the
GSR Register.
1 = Transmit Machine is in idle state.
Note: Idle may indicate that the Transmit Machine (txM) is empty or disabled.
Transmit FIFO Status Functionally identical to the TFIR bit of the GSR Register. It indi-
cates that the Transmit FIFO level is equal to or below the Transmit FIFO Threshold. To dis-
able the transmit FIFO status from being reflected in GIR, either:
• Write a zero to the TFIE bit of the GER Register, or
• Use the Tx FIFO HOLD INTERRUPT logic.
When the TxFIFO is in the hold state, no interrupts are generated, regardless of the TFIR and
TFIE bit settings. The Transmit FIFO enters the hold state when the DPU reads the GIR Reg-
ister and the source of the interrupt is TxFIFO. To exit, the CPU must either set the TFIR bit
of GSR to zero by writing a character to TxFIFO or setting the TFIE bit of GER to zero to dis-
able the Tx FIFO.
BkD
Break Detected Functionally equivalent to the BkD bit of the RST Register.
FE
Framing Error Detected Functionally equivalent to the FE bit of the RST Register.
PE
Parity Error Functionally equivalent to the PE bit of the RST Register.
OE
Overrun Error Functionally equivalent to the OE bit of the RST Register.
Receive FIFO Interrupt Request Functionally identical to the RFIR bit of the GSR Register.
Indicates that the RX FIFO level is above the Rx FIFO threshold. This bit is forced LOW during
any READ from the Rx FIFO. A zero written to this bit acknowledges an Rx FIFO interrupt.
LH75400/01/10/11 (Preliminary) User's Guide
Table 20-27. LSR Register
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
10
9
8
7
0
0
0
0
0
R
R
R
R
R
0xFFFC2000 + 0x14
DESCRIPTION
6/17/03
22
21
20
19
18
0
0
0
0
R
R
R
R
6
5
4
3
TxST TFST BkD
FE
PE
1
1
0
0
RW
RW
RW
RW
RW
17
16
0
0
0
R
R
R
2
1
0
OE
RFIR
0
0
0
RW
RW
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