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LH75400/01/10/11 (Preliminary) User's Guide
16.1 WDT Features .............................................................................................. 16-1
16.2 WDT Theory of Operation ............................................................................ 16-2
16.3 WDT Programmer's Model........................................................................... 16-2
17.1 RTC Features............................................................................................... 17-1
17.2 RTC Theory of Operation ............................................................................. 17-2
17.3 RTC Programmer's Model............................................................................ 17-3
18.1 SSP Features ............................................................................................... 18-1
18.2 SSP Theory Of Operation ............................................................................ 18-3
18.3 SSP Timing Waveforms ............................................................................... 18-4
18.4 Clock Generation.......................................................................................... 18-8
18.5 SSP Programmer's Model.......................................................................... 18-11
16.3.0.1 WDT Register Summary................................................................. 16-2
16.3.1 WDT Register Definitions ...................................................................... 16-3
16.3.1.1 Control Register.............................................................................. 16-3
16.3.1.2 Counter Reset Register .................................................................. 16-4
16.3.1.3 Status Register ............................................................................... 16-5
16.3.1.4 Counter Section 0 Register ............................................................ 16-6
16.3.1.5 Counter Section 1 Register ............................................................ 16-6
16.3.1.6 Counter Section 2 Register ............................................................ 16-7
16.3.1.7 Counter Section 3 Register ............................................................ 16-7
17.3.1 RTC Register Summary ........................................................................ 17-3
17.3.2 RTC Register Definitions ....................................................................... 17-4
17.3.2.1 Data Register 0............................................................................... 17-4
17.3.2.2 Data Register 1............................................................................... 17-5
17.3.2.3 Match Register 0 ............................................................................ 17-6
17.3.2.4 Match Register 1 ............................................................................ 17-6
17.3.2.5 Interrupt Status/Clear ..................................................................... 17-7
17.3.2.6 Read/Write Load Register 0 ........................................................... 17-8
17.3.2.7 Read/Write Load Register 1 ........................................................... 17-9
17.3.2.8 Control Register............................................................................ 17-10
17.3.3 RTC Interrupts ..................................................................................... 17-10
18.3.1 Motorola SPI Frame Format .................................................................. 18-5
18.3.2 Texas Instruments Frame Format ......................................................... 18-7
18.3.3 National Semiconductor Frame Format ................................................ 18-8
18.5.1 SSP Register Summary ...................................................................... 18-11
18.5.2 SSP Register Definitions ..................................................................... 18-12
18.5.2.1 Control Register 0......................................................................... 18-12
18.5.2.2 Control Register 1......................................................................... 18-13
18.5.2.3 Receive / Transmit FIFO Register ................................................ 18-14
18.5.2.4 Status Register ............................................................................. 18-15
18.5.2.5 Clock Prescale Register ............................................................... 18-16
18.5.2.6 Interrupt Identification/Clear Register ........................................... 18-17
18.5.2.7 Receive Timeout Register ............................................................ 18-18
6/17/03
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