Line Control Register; Table 20-19. Lcr Register; Table 20-20. Lcr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.7 Line Control Register

Register Bank: 0
LCR is the Line Control Register. The LCR Register defines the basic configuration of the
serial link.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:8
7
6
5
4
3
2
1
0
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 20-20. LCR Register Definitions

/// Reserved Do not modify. Read as zero.
BAL and BAH Register Access
0 = Denies access to the access to the BAL and BAH Registers in Bank 0, and
DLAB
the BBL and BBH Registers in Bank 3.
1 = Allows access to the access to the BAL and BAH Registers in Bank 0, and
the BBL and BBH Registers in Bank 3.
UART2TX Pin
SBK
1 = Forces the UART2TX pin LOW. The UART2TX pin remains LOW, regardless
of all activities, until this bit is reset.
Parity Mode Works with PM1, PM0, and bit [2] from the Transmit Machine
PM2
Mode Register to define the supported parity mode. See Table 20-21.
Parity Mode Works with PM2, PM0, and bit [2] from the Transmit Machine
PM1
Mode Register to define the supported parity mode. See Table 20-21.
Parity Mode Works with PM2, PM1, and bit [2] from the Transmit Machine
PM0
Mode Register to define the supported parity mode. See Table 20-21.
Stop Bit Length Works with bits [1:0] from the Transmit Machine Mode
SBL0 Register to define the stop-bit length for transmission. The Receive Machine can
identify 3/4 stop bit or more. See Table 20-22.
Character Bit Length Works with CL0 and bit [5]) from the Transmit Machine
CL1
Mode Register to define a character's bit length. See Table 20-23.
Character Bit Length Works with CL1 and bit [5]) from the Transmit Machine
CL0
Mode Register to define a character's bit length. See Table 20-23.

Table 20-19. LCR Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
0 0 0 0
R R R RW
0xFFFC2000 + 0x0C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
SBK PM2 PM1 PM0
0 0 0 0 0
RW RW RW RW RW
UART2
17 16
0 0
R R
1 0
CL1 CL0
0 0
RW RW
20-17