Figure 7-10. Static Read Transaction With Zero Wait States - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
7.2.4.1.1 Read Cycle Wait States
Figure 7-10 shows the Read cycle with zero wait states. As shown in the Figure, SWAIT-
OENx and SWAITRDx (refer to Section 7.5.2.23 and Section 7.5.2.24 for register descrip-
tions) are both programmed to zero, for minimum Read Cycle time. With SWAITOENx
programmed to zero, there is no delay of the nOE signal, and it is asserted coincident with
the nCSx signal. The zero programmed into the SWAITRDx indicates that the read occurs
with zero wait states, on the first rising edge following Address Valid. This time is shown
as 'E0' on the diagram. After a small propagation delay, nOE is deasserted (as is nCSx),
latching the data into the SoC. The address line is held valid one more HCLK period,
denoted by 'C' in the diagram.
NOTES:
With Register Programming:
SWAITOENx = D = 0x0
SWAITRDx = E = 0x0
C = Address hold
Wait states are programmed using the SWAITRDx register. Figure 7-11 shows the results
of programming SWAITRDx ('E') to 0x3, creating three wait states.
In the Figure, Timing A illustrates programming SWAITOENx to 0x0 and SWAITRDx to
0x3. With no wait states, the date would be read on the rising edge of nOE one HCLK cycle
following Address Valid, that time represented by 'E0'. With the wait states, the transaction
is extended by times 'E1', 'E2', and then the data is latched at the conclusion of time 'E3'.
Thus, programming SWAITRDx to 0x3 causes three wait states, each of duration tHCLK
(one HCLK period).
HCLK
A[23:0]
D[31:0]
nCSx
nOE

Figure 7-10. Static Read Transaction with Zero Wait States

Version 1.0
VALID ADDRESS
C
VALID DATA
DATA
LATCHED
E0
External Memory Controller
LH79525-109
7-11