Response Times Of The F_Dp Communication - Siemens SINUMERIK 840D sl Function Manual

Connecting sensors and actuators
8.4 Safety-related CPU-CPU communication (F_DP communication)
● Displaying the maximum F_DP clock cycle
The maximum F_DP clock cycle that has occurred is displayed in MD13322
$MN_INFO_SAFE_SRDP_CYCLE_TIME.
● Incorrect parameterization of the F_DP clock cycle
The lower value of the F_DP clock cycle is not actively limited. When setting the F_DP clock
cycle, the PLC-CPU performance should always be taken into consideration. When
parameterizing an excessively low F_DP clock cycle, Alarm 27353: "F_DP: Actual cycle
time %1 [ms] > parameterized cycle time" is output specifying the currently effective F_DP
clock cycle.
The criterion for an F_DP clock cycle that is set too low is that the parameterized F_DP
clock cycle was exceeded 100 times one after the other.
8.4.7

Response times of the F_DP communication

The response times listed here refer exclusively to the internal processing of the signals by
the F_DP communication layer. The following apply:
● T(FRDP → DB18) or T(FRDP → SPL-INSE)
The transfer time from the input area of the F_RECVDP to the input interface of the PLC-
SPL or NCK-SPL
● T(DB18 → FSDP) or T(SPL-OUTSE → FSDP)
The transfer time from the output interface of the PLC-SPL or NCK-SPL to the output area
of the F_SENDDP.
● T(FRDP → FSDP)
Sum of the transfer times from:
– T(FRDP → DB18) or T(FRDP → SPL-INSE)
–
– T(DB18 → FSDP) or T(SPL-OUTSE → FSDP)
The following applies for the subsequent tables of the PLC and NCK processing times:
● Values in
between the NCK and PLC.
● F_DP clock cycle: 500 ms is the permanently implemented maximum time to detect error-
free communications between the NCK and PLC. A STOP response (STOP D/E) is initiated
if this time is exceeded. The maximum F_DP clock cycle that has occurred is displayed in
MD10091 $MN_INFO_SAFE_SRDP_CYCLE_TIME.
● OB1 clock cycle: 150 ms is the maximum time set as standard in the PLC-CPU to monitor
the user level. The PLC goes into the STOP state if this time is exceeded.
● IPO: IPO clock cycle is formed from MD10050 basic system clock cycle and MD10070
interpolator clock cycle.
● 0...m * IPO clock cycle: This time component only becomes applicable if delays are incurred
on the PLC side. In this case, in each subsequent IPO clock cycle, it is determined as to
whether the PLC is ready to communicate again.
244
Processing time by the user-specific SPL program.
italics can increase by up to 500 ms due to delays in the communication path
Function Manual, 12/2017, 6FC5397-4BP40-6BA1
Safety Integrated