NEC V850E/RS1 User Manual page 89

(on-chip debug reset input)
Caution:
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of the watchdog timer 2.
The watchdog timer 2 automatically starts in the reset mode after reset is released. Write the
WDTM2 register to activate this operation.
For details, refer to Chapter 10 "Functions of Watchdog Timer 2" on page 359.
(3) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hard-
ware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to
the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may
be transferred. If there is a possibility of a conflict, the number of cycles for accessing the CPU
changes when the peripheral hardware is accessed, so that correct data is transferred. As a result,
the CPU does not start processing of the next instruction but enters the wait status. If this wait sta-
tus occurs, the number of clocks required to execute an instruction increases by the number of
wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in
addition to the wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of
CPU clocks) at this time are shown below.
Downloaded from Elcodis.com electronic components distributor
Figure 3-29: Timing Chart of Transition to On-Chip Debug Mode
RESET
(external reset input)
POC
(internal reset)
OCDM0
DRST
To use the on-chip debug function of a product with a power-on clear function, input
a low level to the RESET input pin for 2000 ms or longer after power application.
User's Manual U16702EE3V2UD00
Chapter 3 CPU Function
To use on-chip debug mode by using power-on-clear function,
input external reset longer than power-on-clear detection signal
(internal reset)
On-chip debug mode
OCDM0 bit is cleared to 00
(normal operation mode) by
generation of power-on-clear
detection signal (internal reset)
Normal operation mode
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