NEC V850E/RS1 User Manual page 517

(8) DMA trigger factor register (DTFRn)
The DTFRn register selects the DMA transfer start trigger through interrupt. The interrupt source
selected in this register serves as trigger to start the DMA transfer.
The register can be read or written in 8-bit or 1-bit units. However, only bit 7 (DFn) can be read/
written in 1-bit units.
Initial value is 00H by reset.
Symbol
DTFRn
R/W
Cautions: 1. Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled
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Chapter 15 DMA Functions (DMA Controller)
Figure 15-11: DMA Trigger Factor Register (DTFRn) Format
DTFR0=FFFFFF40H, DTFR1=FFFFFF42H, DTFR2=FFFFFF44H,
DTFR3=FFFFFF46H, DTFR4=FFFFFF48H, DTFR5=FFFFFF4AH
7 6 5
DFn 0 IFCn5
R/W R R/W
DF
0 No DMA transfer request
1 DMA transfer request
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
the next DMA transfer
2. Be sure to follow the steps below when changing the DTFRn register settings.
• When the values to be set to bits IFCn5 to IFCn0 are not set to bits IFCm5 to
IFCm0 of another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Stop the DMAn operation of the channel to be rewritten
(DCHCn.Enn bit = 0).
<2> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and
change the settings in the 8-bit manipulation.)
<3> Confirm that DFn bit = 0. (Stop the interrupt generation source
operation beforehand.)
<4> Enable the DMAn operation (Enn bit = 1).
• When the values to be set to bits IFCn5 to IFCn0 are set to bits IFCm5 to
IFCm0 of another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Stop the DMAn operation of the channel to be rewritten
(DCHCn.Enn bit = 0).
<2> Stop the DMAm operation of the channel where the same values are set
to bits IFCm5 to IFCm0 as the values to be used to rewrite bits IFCn5 to
IFCn0 (DCHCm.Emm bit = 0).
<3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and
change the settings in the 8-bit manipulation.)
<4> Confirm that bits DFn and DFm = 0. (Stop the interrupt generation
source operation beforehand.)
<5> Enable the DMAn operation (bits Enn and Emm = 1).
User's Manual U16702EE3V2UD00
4 3 2 1
IFCn4 IFCn3 IFCn2 IFCn1
R/W R/W R/W R/W
DMA transfer request flag
0 Address After reset
IFCn0 00H
R/W
517