Maskable Interrupts; Operation - NEC V850E/RS1 User Manual

Chapter 17 Interrupt/Exception Processing Function

17.3 Maskable Interrupts

Maskable interrupt requests can be masked by interrupt control registers. The V850E/RS1 has 59
maskable interrupt sources.
If two or more maskable interrupt requests are generated at the same time, they are acknowledged
according to the default priority. In addition to the default priority, eight levels of priorities can be speci-
fied by using the interrupt control registers (programmable priority control).
When an interrupt request has been acknowledged, the acknowledgement of other maskable interrupt
requests is disabled and the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is
set, which enables servicing of interrupts having a higher priority than the interrupt request in progress
(specified by the interrupt control register). Note that only interrupts with a higher priority will have this
capability; interrupts with the same priority level cannot be nested.
To enable multiple interrupts, however, save EIPC and EIPSW to memory or registers before executing
the EI instruction, and execute the DI instruction before the RETI instruction to restore the original val-
ues of EIPC and EIPSW.

17.3.1 Operation

If a maskable interrupt occurs by INT input, the CPU performs the following processing, and transfers
control to a handler routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower half-word of ECR (EICC).
<4> Sets the ID bit of the PSW and clears the EP bit.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request masked by INTC and the maskable interrupt request generated while
another interrupt is being serviced (while PSW.NP = 1 or PSW.ID = 1) are held pending inside INTC. In
this case, servicing a new maskable interrupt is started in accordance with the priority of the pending
maskable interrupt request if either the maskable interrupt is unmasked or PSW.NP and PSW.ID are
cleared to 0 by using the RETI or LDSR instruction.
How maskable interrupts are serviced is illustrated below.
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