NEC V850E/RS1 User Manual page 840

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Mnemonic
RETI
SAR
SASF
SATADD
SATSUB
SATSUBI imm16,reg1,reg2
SATSUBR reg1,reg2
SETF
SET1
SHL
SHR
SLD.B
SLD.BU
SLD.H
SLD.HU
SLD.W
SST.B
SST.H
SST.W
ST.B
ST.H
ST.W
STSR
SUB
SUBR
840
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Appendix A
Operand Opcode
0000011111100000
0000000101000000
rrrrr111111RRRRR
reg1,reg2
0000000010100000
imm5,reg2
rrrrr010101iiiii
rrrrr1111110cccc
cccc,reg2
0000001000000000
reg1,reg2 rrrrr000110RRRRR GR[reg2]←saturated(GR[reg2]+GR[reg1])
imm5,reg2 rrrrr010001iiiii GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)
reg1,reg2 rrrrr000101RRRRR GR[reg2]←saturated(GR[reg2]–GR[reg1])
rrrrr110011RRRRR
iiiiiiiiiiiiiiii
rrrrr000100RRRRR GR[reg2]←saturated(GR[reg1]–GR[reg2])
rrrrr1111110cccc
cccc,reg2
0000000000000000
00bbb111110RRRRR
bit#3,disp16[reg1]
dddddddddddddddd
rrrrr111111RRRRR
reg2,[reg1]
0000000011100000
rrrrr111111RRRRR
reg1,reg2
0000000011000000
imm5,reg2
rrrrr010110iiiii
rrrrr111111RRRRR
reg1,reg2
0000000010000000
imm5,reg2
rrrrr010100iiiii
disp7[ep],reg2
rrrrr0110ddddddd
rrrrr0000110dddd
disp4[ep],reg2
Note 18
rrrrr1000ddddddd
disp8[ep],reg2
Note 19
rrrrr0000111dddd
disp5[ep],reg2
Notes 18, 20
rrrrr1010dddddd0
disp8[ep],reg2
Note 21
reg2,disp7[ep]
rrrrr0111ddddddd
rrrrr1001ddddddd
reg2,disp8[ep]
Note 19
rrrrr1010dddddd1
reg2,disp8[ep]
Note 21
rrrrr111010RRRRR
reg2,disp16[reg1]
dddddddddddddddd
rrrrr111011RRRRR
reg2,disp16[reg1]
ddddddddddddddd0
Note 8
rrrrr111011RRRRR
reg2,disp16[reg1]
ddddddddddddddd1
Note 8
rrrrr111111RRRRR
regID,reg2
0000000001000000
reg1,reg2 rrrrr001101RRRRR GR[reg2]←GR[reg2]–GR[reg1]
reg1,reg2 rrrrr001100RRRRR GR[reg2]←GR[reg1]–GR[reg2]
Instruction Set List
Operation
if PSW.EP=1
then PC ←EIPC
PSW ←EIPSW
else if PSW.NP=1
then PC ←FEPC
PSW ←FEPSW
else PC←EIPC
PSW ←EIPSW
GR[reg2]←GR[reg2] arithmetically shift right
by GR[reg1]
GR[reg2]←GR[reg2] arithmetically shift right
by zero-extend (imm5)
if conditions are satisfied
then GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000000H
GR[reg2]←saturated(GR[reg1]–sign-extend(imm16)
If conditions are satisfied
then GR[reg2]←00000001H
else GR[reg2]←00000000H
adr←GR[reg1] + sign-extend(disp16)
Z flag←Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
GR[reg2]←GR[reg2] logically shift left by GR[reg1]
GR[reg2]←GR[reg2] logically shift left by
zero-extend(imm5)
GR[reg2]←GR[reg2] logically shift right by GR[reg1]
GR[reg2]←GR[reg2] logically shift right by
zero-extend(imm5)
adr←ep + zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
adr←ep + zero-extend(disp4)
GR[reg2]←zero-extend(Load-memory(adr,Byte))
adr←ep + zero-extend(disp8)
GR[reg2]←sign-extend(Load-memory(adr,Half-word))
adr←ep+zero-extend(disp5)
GR[reg2]←zero-extend(Load-memory(adr,Half-word))
adr←ep + zero-extend(disp8)
GR[reg2]←Load-memory(adr,Word)
adr←ep + zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
adr←ep + zero-extend(disp8)
Store-memory(adr,GR[reg2],Half-word)
adr←ep + zero-extend(disp8)
Store-memory(adr,GR[reg2],Word)
adr←GR[reg1] + sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
adr←GR[reg1] + sign-extend(disp16)
Store-memory (adr,GR[reg2], Half-word)
adr←GR[reg1] + sign-extend(disp16)
Store-memory (adr,GR[reg2], Word)
GR[reg2]←SR[regID]
User's Manual U16702EE3V2UD00
Execution
Flags
Clock
i r l CY OV S Z SAT
3 3 3 R R R R R
× × ×
1 1 1 0
× × ×
1 1 1 0
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
× × × × ×
1 1 1
1 1 1
3 3 3
×
Note Note Note
3 3 3
3 3 3
×
Note Note Note
3 3 3
× × ×
1 1 1 0
× × ×
1 1 1 0
× × ×
1 1 1 0
× × ×
1 1 1 0
Note
1 1
9
Note
1 1
9
Note
1 1
9
Note
1 1
9
Note
1 1
9
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
× × × ×
1 1 1
× × × ×
1 1 1