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(3)
PLL lockup time specification register (PLLS)
The PLLS register is an 8-bit register used to select the PLL lockup time when the PLL is initialized
by writing the value 00H to the PLLCTLn register, and when the software STOP mode is released.
This register can be read or written in 8-bit units.
Reset input sets this register to 03H.
Symbol
PLLS
R/W
PLLS1
0
0
1
1
Remark:
Caution:
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Chapter 6 Clock Generator
Figure 6-12: PLL Lockup Time Specification Register (PLLS)
7
6
5
4
0
0
0
0
R
R
R
R
PLLS0
10
0
2
/f
(128 µs)
X
11
1
2
/f
(256 µs)
X
12
0
2
/f
(512 µs)
X
13
1
2
/f
(1024 µs) (default)
X
The value in parentheses assumes an 8 MHz external oscillator frequency (f
Always set PLLS so that the interval time is 800 µs or longer.
User's Manual U16702EE3V2UD00
3
2
1
0
0
0
PLLS1
PLLS0
R
R
R/W
R/W
PLL lockup time selector
Address
After reset
FFFFF6C1H
03H
).
X
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