NEC V850E/RS1 User Manual page 512

Remark:
Please refer to 15.5 on page 522 and Table 15-3 on page 524 for details on and a comparison of the
transfer modes.
TDIR bit = 0
Source address: DMSAn register
Source object: TS1 & 0 bit
Source address count: SAD bit
TDIR bit = 1
Source address: DMDAn register
Source object: TD1 & 0 bit
Source address count: DAD bit
512
Downloaded from Elcodis.com electronic components distributor
Chapter 15 DMA Functions (DMA Controller)
Figure 15-8: DMA Addressing Control Register (DMADCn) Format (2/2)
DAD Destination Address Count Mode (DA[25:0] bits)
0 Destination address is incremented after each transfer.
1 Destination address is fixed
DS1 DS0
0 0 Byte (8-bit)
0 1 Half word (16-bit)
1 0 Word (32-bit)
1 1 Setting prohibited
If address incrementation is selected for the source address and/or the destination address,
the address is incremented based on the DMA transfer size. For 8-bit size, the address is
incremented by 1, for 16-bit by 2, and for 32-bit by 4.
TM1 TM0
0 0 Single transfer mode (starting value)
0 1 Fixed Channel transfer mode
1 0 Setting prohibited
1 1 Block transfer mode
TDIR
Transfer from source → destination
0
Transfer from destination → source
1
Figure 15-9: Effect of TDIR Flag on DMA Transfer
User's Manual U16702EE3V2UD00
Selected DMA Transfer Size
Selected DMA Transfer Mode
DMA Transfer Direction
Destination address: DMDAn register
Destination object: TD1 & 0 bit
DMA transfer
Destination address count: DAD bit
Destination address: DMSAn register
Destination object: TS1 & 0 bit
DMA transfer
Destination address count: SAD bit