Control Register - NEC V850E/RS1 User Manual

22.3 Control Register

(1) On-chip debug mode register (OCDM)
This register is used to select the normal operation mode or on-chip debug mode. This is a special
register (refer to 3.2.3 "Special registers" on page 70). It can be written only in a specific
sequence so that its contents cannot be rewritten by mistake in the case of a program loop.
If the OCDM0 bit is 1 and if the DRST pin is high, the on-chip debug mode is selected.
The default value of the OCDM0 bit after the pin is reset is 1. It is therefore necessary to clear the
OCDM0 bit to 0 when the on-chip debug function is not used, and until then, the DRST pin must
be kept low (see Figure 22-4). The DRST pin is internally pulled down while the OCDM0 bit is 1,
and therefore, it may be left open.
After POC reset, the default value of the OCDM1 bit is 0, and the normal operation mode is
selected.
Therefore, it is necessary to set the OCDM0 bit to 1 by resetting the pin to use the on-chip debug
mode.
If POC reset occurs during on-chip debugging, communication with the emulator is disrupted.
Therefore, POC reset cannot be emulated (see Figure 22-5).
This register can be read or written in 8-bit or 1-bit units.
Symbol
OCDM
R/W
Notes: 1. On input to RESET pin (external reset): OCDM0 = 1
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Chapter 22 On-Chip Debug Function
Figure 22-2: On-Chip Debug Mode Register (OCDM) Format
7 6 5
0 0 0
R R/W R/W
OCDM0
Specification of alternate-function pin of on-chip debug function
0 Used as port/peripheral function pin
1 Used as on-chip debug pin
On reset by power-on clear: OCDM0 = 0
On occurrence of internal source reset (other than power-on clear): The OCDM register
holds the value before occurrence of reset.
2. P97/SIB1/{DDI}
P98/SOB1/{DCK
P99/SCKB1/{DMS}
P910/CS301/{DDO}
P911/{DRST}
User's Manual U16702EE3V2UD00
4 3 2 1
0 0 0 0
R/W R R R
0 Address After reset
Note 1
OCDM0 FFFFF9FCH
01H
R/W
Note 2
771