Cautions - NEC V850E/RS1 User Manual

3.4.7 Cautions

(1) Registers to be set first
Be sure to set the following registers first when using the V850E/RS1.
• System wait control register (VSWC)
• On-chip Debug Mode control register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the
port-related registers after setting the above registers.
(2) Area access time (VSWC) and On chip debug mode control register (OCDM)
(a) System wait control register (VSWC)
The system wait control register (VSWC) controls wait of bus access to the internal peripheral I/O
registers.
Three clocks are required to access an internal peripheral I/O register (without a wait cycle). The
V850E/RS1 requires wait cycles according to the operating frequency. Set the following value to
the VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units.
Symbol
VSWC
R/W
Caution:
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Chapter 3 CPU Function
Figure 3-25: System Wait Control Register (VSWC) Format
7 6 5 4
0 SUWL2 SUWL1 SUWL0
R R/W R/W R/W
Operation Frequency (f
4 MHz ≤ φ ≤ 25 MHz
25 MHz ≤ φ ≤ 33 MHz
33 MHz ≤ φ ≤ 40 MHz
Only select a value that corresponds to a supported operating frequency.
User's Manual U16702EE3V2UD00
3 2 1
0 VSWL2 VSWL1 VSWL0
R R/W R/W
)
VSWC setting
XX
11H
12H
14H
0 Address After reset
FFFFF06EH 77H
R/W