Pwm Mode (Tqnmd2 To Tqnmd0 = 110) - NEC V850E/RS1 User Manual

8.5.6 PWM mode (TQnMD2 to TQnMD0 = 110)

In the PWM mode, TMQn capture/compare register k (TQnCCRk) is used to set the duty factor and
TMQn capture/compare register 0 (TQnCCR0) is used to set the cycle.
By using these two registers and operating the timer, variable-duty PWM is output.
Rewriting the TQnCCRm register is enabled when TQnCE = 1.
So that the set value of the TQnCCRm register is compared with the value of the 16-bit counter
(reloaded to the CCRm buffer register), the TQnCCR0 register must be rewritten and then a value must
be written to the TQnCCR1 register before the value of the 16-bit counter matches the value of the
TQnCCR0 register. The value of the TQnCCRm register is reloaded when the value of the TQnCCR0
register later matches the value of the 16-bit counter.
Whether the next reload timing is made valid or not is controlled by writing to the TQnCCR1 register.
Therefore, write the same value to the TQnCCR1 register even when only the value of the TQnCCR0
register needs to be rewritten. Reload is invalid when only the value of the TQnCCR0 register is
rewritten.
To stop timer Q, clear TQnCE to 0. The waveform of PWM is output from the TOQnk pin.
The TOQn0 pin produces a toggle output when the 16-bit counter matches the TQnCCR0 register.
In the PWM mode, the TQnCCRm register is used only as a compare register. It cannot be used as a
capture register.
Remark:
Downloaded from Elcodis.com electronic components distributor
Chapter 8 16-Bit Timer/Event Counter Q
n = 0 to 1
m = 0 to 3
k = 1 to 3
User's Manual U16702EE3V2UD00 337