NEC V850E/RS1 User Manual page 507

(2) DMA channel status flag register (DMSF)
The DMSF register shows the DMA transfer status of each DMA channel. It is a direct mirror of all
ACF bits (DMCHCn register). It can be read in 16-bit units only.
The register is initialized by POWER = 0. Initial value is 0000H by reset.
DMSF
R/W
Refer to (7)"DMA channel control register (DMCHCn)" on page 513 for the explanation of the ACF
bits.
(3) DMA source address register (DMSAn)
The DMSAn register is used to set the DMA source address. When the TDIR bit (DMADCn regis-
ter) is 0, it holds the address the data is transferred from (source), for TDIR=1 the register holds
the address data is transferred to (destination). The register can be read or written in 32-bit or 16-
bit units.
Caution:
DMSAnH SC2 SC1 SC0
R/W
DMSAnL SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
R/W
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Chapter 15 DMA Functions (DMA Controller)
Figure 15-4: DMA Channel Status Flag Register (DMSF) Format
15 14 13 12 11 10
0 0 0 0 0 0
R R R R R R
Write to DMSAn is permitted only when EN = 0 (DMCHCn register).
Figure 15-5: DMA Source Address Register (DMSAn) Format (1/2)
DMSA0H=FFFFFE0AH, DMSA1H=FFFFFE16H, DMSA2H=FFFFFE22H,
DMSA3H=FFFFFE2EH, DMSA4H=FFFFFE3AH, DMSA5H=FFFFFE46H
15 14 13 12 11 10
0 0 0
R/W R/W R/W R R R
DMSA0L=FFFFFE08H, DMSA1L=FFFFFE14H, DMSA2L=FFFFFE20H,
DMSA3L=FFFFFE2CH, DMSA4L=FFFFFE38H, DMSA5L=FFFFFE44H
15 14 13 12 11 10
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
User's Manual U16702EE3V2UD00
9 8 7 6 5 4
ACF ACF
0 0 0 0
(ch5) (ch4)
R R R R R R
9 8 7 6 5 4
SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
9 8 7 6 5 4
3 2 1 0 Address
ACF ACF ACF ACF
FFFFFE04H
(ch3) (ch2) (ch1) (ch0)
R R R R
3 2 1 0 Address
3 2 1 0 Address
After
reset
0000H
After
reset
undef.
After
reset
undef.
507