Usage; To Use Pll1; Table 6-1: Divide And Pll0 Time Value; Table 6-2: Divide And Pll1 Time Value - NEC V850E/RS1 User Manual

6.6 Usage

6.6.1 To use PLL1

After RESET has been released, the default mode is PLL0 mode (F
operating mode change to PLL1 mode, register access must keep below mentioned order.
• (When use PLL1 function as master clock and PLL0 for peripheral clock)
1) Setting OCKS1 register
2) Setting CKC register
3) PLLCTL1 register =
4) MPCCTL register =
4) MPCCTL register =
5) MPCCTL register <= 88H write (MPCCTL: SELPLL bit = MCKSEL bit =1)
• (When use PLL1 function as master clock and peripheral clock)
1) Setting OCKS1 register
2) Setting CKC register
3) PLLCTL1 register =
4) MPCCTL register =
4) MPCCTL register =
5) MPCCTL register <= 8DH write (MPCCTL: SELPLL bit = MCKSEL bit = PCKSEL bit =
STPPLL0 bit = 1)
Caution:
The follow table shows the divide and PLL0 time value.
OCKS0 register (h)
12h
11h (Default)
18h
The follow table shows the divide and PLL1 time value.
OCKS1 register (h)
10h (Default)
18h
252
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Chapter 6 Clock Generator
00H write
00H write
08H write (MPCCTL: MCKSEL bit = 1)
00H write
00H write
08H write (MPCCTL: MCKSEL bit = 1)
Before using the STOP/IDLE mode for power saving operation, the user must first
reduce CPU operating frequency to 20 MHz using PCC register.

Table 6-1: Divide and PLL0 Time Value

CKC register (h)
03h
03h (Default)
02h

Table 6-2: Divide and PLL1 Time Value

CKC register (h)
03h
03h
03h
User's Manual U16702EE3V2UD00
PLL_MCKSEL
(MPCCTL: SELPLL bit = 0)
(MPCCTL: SELPLL bit = 0)
PLL time value
Xtal = 4 MHz
3 12
4 16
6 24
PLL time value
Xtal = 4 MHz
2 8
5 20
10 40
= 4 × f
). When
X
f (MHz)
X
Xtal = 6 MHz Xtal = 8 MHz
18 24
24 32
Setting
36
prohibited
f (MHz)
X
Xtal = 6 MHz Xtal = 8 MHz
12 16
30 40
Setting Setting
prohibited prohibited