NEC V850E/RS1 User Manual page 501

(11) FIFO Buffer Transfer Mode (Slave Mode, Receive Only Mode)
MSB first (DIR = 0), no INTC3nI delay (CSIT = 0), transmission wait disabled (CSWE = 0), CS
inactive disabled (CSMD = 0), CKP = 0, DAP = 0, transmission data length of 8 bits
(CCL[3:0] = [1,0,0,0]), active levels of all chip selects set to "active low":
SFDB write
CSIB
CSIBUF_0
CSIBUF_1
CSIBUF_2
SCK3 (input)
SIRB read
1. Set the CSIM register's POWER bit to 1 to enable the supply of the Queued CSI operation clock.
2. Set the CSIC and CSIL registers to specify the transfer mode.
3. Write "1" in the SFA register's FPCLR bit to clear all FIFO pointers.
4. Specify the transfer mode using the CSIM register's TRMD, DIR, and CSIT bits; at the same time,
set the CRXE bit to 1 to enable the receive operation.
5. Set the number of receive-data items in the SFN register's SFN[3:0] bits.
6. Make sure that the SFA register's SFFUL bit is set to 0, then write dummy transmission data in the
SFDB register (start-of-receive trigger). (In the slave mode, there is no need to set data in the
SFCS register, as the chip select pins CS3n[3:0] are not used.)
7. Wait for the receptions to be completed (e.g. by monitoring the INT3C3nI interrupt).
8. Read the received data by multiple read of the SIRB register (= sequential read from the FIFO).
9. Write "1" in the SFA register's FPCLR bit and clear all FIFO pointers for the next transmission.
To continue reception, repeat steps (5) - (9).
10. Set the CSIM register's CRXE bit to 0 to disable the receive operation (end of receive operation).
Remark:
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Chapter 14 Queued CSI (CSI30, CSI31)
Figure 14-35: FIFO Buffer Transfer Mode (Slave, Receive Only) Timing
CRXE
UF-empty
dummy
SI3
0
1 0 1 0
"inactive level"
CS3n[3:0]
CSOT
INTC3nI
SFN3-0
3H
SFP3-0 0H
(1) (2)(3)
(5) (6)
(4)
(6)
The SO3n pin is invalid and maintains its signal level, as the output latch is disabled.
User's Manual U16702EE3V2UD00
55H
dummy
1 0 1 1 0 1 0 1 0 1 0
1H 2H
Wait insertion
by CSIBUF-empty
AAH
dummy
CCH
0 0
1 1 0 0 1 1
3H
(6)
(7)
(8)
0H
(8)
(10)
(9)
(8)
501