Bus Priority; Boundary Operation Conditions; Program Space; Data Space - NEC V850E/RS1 User Manual

5.8 Bus Priority

Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are
executed in the external bus cycle.
Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and
instruction fetch (successive).
An instruction fetch may be inserted between the read access and write access in a read-modify-write
access.
If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted
between accesses due to bus size limitations.

5.9 Boundary Operation Conditions

5.9.1 Program space

(1) If a branch instruction exists at the upper limit of the internal RAM area, a prefetch operation
straddling over the internal peripheral I/O area (invalid fetch) does not occur.
(2) Instruction execution to the external memory area cannot be continued without a branch from the
internal ROM area to the external memory area.

5.9.2 Data space

The V850E/RS1 has an address misalign function.
With this function, data can be placed at all addresses, regardless of the format of the data (word data
or halfword data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle
is generated at least twice, causing the bus efficiency to drop.
(1) Halfword-length data access
A byte-length bus cycle is generated twice if the least significant bit of the address is 1.
(2) Word-length data access
(a) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in
(b) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
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Chapter 5 Bus Control Function
Priority
High Bus hold
DMA transfer
Operand data access
Instruction fetch (branch)
Instruction fetch (successive)
Low
that order if the least significant bit of the address is 1.
User's Manual U16702EE3V2UD00

Table 5-4: Bus Priority

External Bus Cycle
External device
DMAC
CPU
CPU
CPU
Bus Master
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