NEC V850E/RS1 User Manual page 267

(6) TMPn option register 0 (TPnOPT0)
The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect
overflow.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
Symbol
TPnOPT0
TPnCCS1
The TPnCCS1 bit setting is valid only in the free-running mode.
TPnCCS0
The TPnCCS0 bit setting is valid only in the free-running mode.
Set (1)
Reset (0)
• The TPnOVF bit is reset when the 16-bit counter value overflows from FFFFH to 0000H in the free-
• An interrupt request signal (INTTPnOV) is generated as soon as TPnOVF bit is set (1).
• The TPnOVF bit is not cleared even when the TPnOVF bit and the TPnOPT0 register are read when
• The TPnOVF bit can be both read and written, but 1 cannot be written to the TPnOVF bit from the
Caution:
Remark:
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Chapter 7 16-Bit Timer/Event Counter P
Figure 7-10: TMPn Option Register 0 (TPnOPT0) Format
Address: TP0OPT0: FFFFF595H, TP1OPT0: FFFFF5A5H
TP2OPT0: FFFFF5B5H, TP3OPT0: FFFFF5C5H
7 6 5
0 0 TPnCCS1 TPnCCS0
0 Compare register selection
1 Capture register selection
0 Compare register selection
1 Capture register selection
TPnOVF
Overflow occurrence
TPnOVF bit write or TPnCE = 0
running mode and the pulse width measurement mode.
The INTTPnOV signal is not generated in any mode other than free-running mode and the pulse width
measurement mode.
TPnOVF = 1.
CPU. Writing 1 has no influence on timer P operation.
Rewrite TPnCCS1 and TPnCCS0 bits when TPnCE = 0 (the same value can be written
when TPnCE = 1.). If rewriting was mistakenly performed, clear TPnCE to 0 and then
set the bits again.
n = 0 to 3
User's Manual U16702EE3V2UD00
4 3 2 1
0 0 0
TPnCCR1 register capture/compare selection
TPnCCR0 register capture/compare selection
Timer P overflow detection
<0> Address R/W
FFFFF595H
TPnOVF to R/W 00H
FFFFF5C5H
After
reset
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