Queued Csi Block Diagram; Input/Output Pins; Table 14-1: Input/Output Pins Of The Csi3 - NEC V850E/RS1 User Manual

14.1.1 Queued CSI Block Diagram

14.1.2 Input/Output Pins

The table below shows the input/output pins of the CSI3.
Notes: 1. n = 0, 1
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Chapter 14 Queued CSI (CSI30, CSI31)
Figure 14-1: Queued CSI Block Diagram
BRG
SEL
SCK3n
SO3n
SI3n
CS3n0
CS3n1
CS3n2
CS3n3

Table 14-1: Input/Output Pins of the CSI3

Signal
I/O Active level
name
SCK3n I/O –
SI3n I –
SO3n O –
Note 2
CS3n0 O
L
Note 2
CS3n1 O
L
Note 2
CS3n2 O
L
Note 2
CS3n2 O
L
2. The active level is programmable for each chip select.
NPB (NEC Peripheral Bus)
16 x 2
19
Window Register
20
19
FIFO
20 bits x 16 elements
16
4
SIO
16
Rx Buffer
CS
Control
16
Disabled level
H Serial clock signal
– Input serial data signal
– Output serial data signal
Note 2
Serial peripheral chip select signal
H
Note 2
Serial peripheral chip select signal
H
Note 2
Serial peripheral chip select signal
H
Note 2
Serial peripheral chip select signal
H
User's Manual U16702EE3V2UD00
0
0
INTC3nO
Full
Flag
Pointer
INTC3nI
Function