Table 18-3: Operation Status In Halt Mode - NEC V850E/RS1 User Manual

(2) Releasing HALT mode by RESET pin input
The same operation as the normal reset operation is performed.
Item
Main clock oscillator (f
Ring clock generator (f
PLL
Flash charge pump
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP3)
Timer Q (TMQ0, TMQ1)
Timer M (TMM0)
Watchdog timer 2 (WDT2)
Serial
interface
AFCAN0, AFCAN1
A/D converter
External bus interface
Port function
Internal data
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Chapter 18 Standby Function

Table 18-3: Operation Status in HALT Mode

Setting of HALT Mode
)
Oscillation enabled
X
)
Oscillation enabled
R
Operable
Continues operation
Stops operation
Operable
Operable
Operable
Operable
Operable
Operable
CSIB0, CSIB1 Operable
UARTA0, UARTA1 Operable
CSI30, CSI31 Operable
Operable
Operable
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Retains status before HALT mode was set.
The CPU registers, statuses, data, and all other internal data such as the
contents of the internal RAM are retained as they were before the HALT
mode was set.
User's Manual U16702EE3V2UD00
Operation Status