NEC V850E/RS1 User Manual page 22

32-/16-bit single-chip microcontroller with can interface
Table of Contents

Advertisement

Figure 12-12:
Figure 12-13:
Figure 12-14:
Figure 12-15:
Figure 12-16:
Figure 12-17:
Figure 12-18:
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
Figure 13-5:
Figure 13-6:
Figure 13-7:
Figure 13-8:
Figure 13-9:
Figure 13-10:
Figure 13-11:
Figure 13-12:
Figure 13-13:
Figure 13-14:
Figure 13-15:
Figure 13-16:
Figure 13-17:
Figure 13-18:
Figure 13-19:
Figure 13-20:
Figure 13-21:
Figure 13-22:
Figure 13-23:
Figure 13-24:
Figure 13-25:
Figure 13-26:
Figure 14-1:
Figure 14-2:
Figure 14-3:
Figure 14-4:
Figure 14-5:
Figure 14-6:
Figure 14-7:
Figure 14-8:
Figure 14-9:
Figure 14-10:
Figure 14-11:
Figure 14-12:
Figure 14-13:
Figure 14-14:
Figure 14-15:
Figure 14-16:
Figure 14-17:
Figure 14-18:
Figure 14-19:
Figure 14-20:
Figure 14-21:
Figure 14-22:
Figure 14-23:
Figure 14-24:
Figure 14-25:
22
Downloaded from
Elcodis.com
electronic components distributor
Timing of Continuous Transmission Operation ......................................................... 419
UART Reception........................................................................................................ 420
Receive Data Read Flow........................................................................................... 421
Noise Filter Circuit ..................................................................................................... 424
Configuration of Baud Rate Generator ...................................................................... 425
Permissible Baud Rate Range for Reception ............................................................ 428
Transfer Rate for Continuous Transmission.............................................................. 430
Block Diagram of 3-Wire Serial Interface .................................................................. 432
CSIBn Control Register 0 (CBnCTL0) Format (1/2) ................................................. 434
CSIBn Control Register 1 (CBnCTL1) Format (1/2) ................................................. 436
CSIBn Control Register 2 (CBnCTL2) Format .......................................................... 438
CSIBn Status Register (CBnSTR) Format ................................................................ 439
CSIBn Receive Data Register (CBnRX) Format ...................................................... 440
CSIBn Transmit Data Register (CBnTX) Format ...................................................... 440
Changing Transfer Data Length ................................................................................ 441
Single Transfer Timing (Master Mode, Transmission/Reception Mode) ................... 443
Single Transfer Timing (Master Mode, Reception Mode).......................................... 444
Continuous Transfer Timing (Master Mode, Transmission/Reception Mode) ........... 445
Continuous Transfer Timing (Master Mode, Reception Mode).................................. 446
Continuous Transfer Timing (Error)........................................................................... 447
Continuous Transfer Timing (Slave Mode, Transmission/Reception Mode) ............. 448
Continuous Transfer Timing (Slave Mode, Reception Mode).................................... 449
Clock Timing (1/2) ..................................................................................................... 450
Single Transmission Flow.......................................................................................... 453
Single Reception Flow (Master) ................................................................................ 454
Single Transmission/Reception Flow (Master) .......................................................... 455
Single Reception Flow (Slave) .................................................................................. 456
Continuous Transmission Flow ................................................................................. 457
Continuous Reception Flow (Master) ........................................................................ 458
Continuous Transmission/Reception Flow (Master).................................................. 459
Continuous Reception Flow (Slave) .......................................................................... 460
Prescaler Mode Register 0 (PRSM0) Format ........................................................... 461
Prescaler Compare Register 0 (PRSCM0) Format .................................................. 462
Queued CSI Block Diagram ...................................................................................... 464
Queued CSI Operation Mode Registers (CSIM0, CSIM1) Format (1/2) ................... 466
Queued CSI Clock Selection Registers (CSIC0, CSIC1) Format (1/2) .................... 468
Queued CSI Baud Rate Block Diagram .................................................................... 470
Receive Data Buffer Registers (SIRB0, SIRB1) Format ........................................... 471
Chip Select Data Buffer Registers (SFCS0, SFCS1) Format ................................... 471
Transmission Data Buffer Registers (SFDB0, SFDB1) Format ................................ 472
FIFO Buffer Status Registers (SFA0, SFA1) Format (1/2) ....................................... 472
Queued CSI Data Length Selection Registers (CSIL0, CSIL1) Format ................... 474
Queued CSI Transfer Number Selection Registers (SFN0, SFN1) Format ............. 475
Transmit Buffer .......................................................................................................... 476
Serial Data Direction Select Function........................................................................ 477
Data Length Select Function ..................................................................................... 478
Slave Mode................................................................................................................ 479
Master Mode.............................................................................................................. 479
Transfer Clock Select Function ................................................................................. 480
Single Buffer Transfer Mode Data Handling.............................................................. 481
Single Buffer Transfer Mode (Master, Transmit/Receive) Timing ............................. 482
FIFO Buffer Transfer Mode Data Handling................................................................ 483
FIFO Buffer Transfer Mode (Master, Transmit/Receive) Timing ............................... 484
Delay Selection of Receive Termination Interrupt (INTC3nI) .................................... 486
Selection of Transmit Wait Enable/Disable ............................................................... 487
Selection of Chip-Select Mode .................................................................................. 488
Transmit Buffer Overflow Interrupt Signal (INTC3nO)............................................... 490
Single Buffer Transfer Mode (Master, Transmit Only) Timing ................................... 491
User's Manual U16702EE3V2UD00

Advertisement

Table of Contents
loading

Table of Contents