NEC V850E/RS1 User Manual page 511

(6) DMA addressing control register (DMADCn)
The DMADCn register control the address handling for each DMA channel. It can be read or writ-
ten in 8-bit or 16-bit units.
Initial value is F000H by reset.
Caution:
Symbol
DMADCnH
Reset value
R/W
Symbol
DMADCnL
Reset value
R/W
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Chapter 15 DMA Functions (DMA Controller)
Write to DMADCn is permitted only when EN = 0 (DMCHCn register).
Figure 15-8: DMA Addressing Control Register (DMADCn) Format (1/2)
DMADC0H=FFFFFE13H, DMADC1H=FFFFFE1FH, DMADC2H=FFFFFE2BH,
DMADC3H=FFFFFE37H, DMADC4H=FFFFFE43H, DMADC5H=FFFFFE4FH
7 6 5
TS1 TS0 TD1
1 1 1
R/W R/W R/W
DMADC0L=FFFFFE12H, DMADC1L=FFFFFE1EH, DMADC2L=FFFFFE2AH,
DMADC3L=FFFFFE36H, DMADC4L=FFFFFE42H, DMADC5L=FFFFFE4EH
7 6 5
DS1 DS0 0
0 0 0
R/W R/W R
TS1 TS0
0 0 Source address is external I/O
0 1 Setting prohibited
1 0 Source address is Internal RAM
1 1 Source address is on-chip peripheral I/O
TD1 TD0
0 0 Destination address is external I/O
0 1 Setting prohibited
1 0 Destination address is internal RAM
1 1 Destination address is on-chip peripheral I/O
SAD Source Address Count Mode (SA[25:0] bits)
0 Source address is incremented after each transfer.
1 Source address is fixed
User's Manual U16702EE3V2UD00
4 3 2 1
TD0 SAD 0 DAD
1 0 0 0
R/W R/W R R/W
4 3 2 1
0 TM1 TM0 0
0 0 0 0
R R/W R/W R
Source Address Area Selector (SA[25:0] bits)
Destination Address Area Selector (DA[25:0] bits)
0 Address After reset
0 F0H
0
R
0 Address After reset
TDIR 00H
0
R/W
511