Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 = 110) - NEC V850E/RS1 User Manual

7.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110)

In the pulse width measurement mode, free-running count is performed, and upon detection of
both the rising and falling edges of TIPn0, the 16-bit counter value is saved to capture register 0
(TPnCCR0) and the 16-bit counter is cleared to 0000H. The external input pulse width can be
measured as a result.
However, when measuring a large pulse width that exceeds 16-bit counter overflow, perform
judgment with the overflow flag. Since measurement of pulses for which overflow occurs twice or
more is not possible, adjust the operating frequency of the 16-bit counter. The value of the 16-bit
counter is also saved to capture register 1 (TPnCCR1) and the 16-bit counter cleared upon
detection of the TIPn1 edge.
Caution:
Note: An external pulse can be input from either TIPn0 or TIPn1. Only one of them can be used.
Remark:
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Chapter 7 16-Bit Timer/Event Counter P
In the pulse width measurement mode, select the internal clock (TPnEEE of TPnCTL1
register = 0).
Figure 7-32: Flowchart of Basic Operation in Pulse Width Measurement Mode
•
•
•
Specify that both the rising and falling edges are detected. Specify that the input edge of an
external pulse input that is not used is not detected.
n = 0 to 3
m = 0, 1
User's Manual U16702EE3V2UD00
START
Initial settings
Clock selection
(TPnCTL0: TPnCKS2 to TPnCKS0)
Pulse width measurement mode setting
(TPnCTL1: TPnMD2 to TPnMD0 = 110)
Compare register setting
(TPnCCR0, TPnCCR1)
TIPn1/TIPn0 edge detection setting
(TPnIS3 to TPnIS0)
Timer operation enable (TPnCE = 1)
Rising edge input to TIPnn, capture of
value to TPnCCRn, 16-bit counter clear
& start
Falling edge input to TIPnn, capture of
value to TPnCCRn, 16-bit counter clear
& start
Note
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