NEC V850E/RS1 User Manual page 249

(6) Clock selection register 1 (OCKS1)
This is an 8-bit register that controls the operation enable and clock input selection for PLL1.
Symbol
OCKS1
R/W
OCKSEN1
OCKSTH1
Caution:
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Figure 6-15: Clock Selection Register 1 (OCKS1) Format
7 6 5
0 0 0 OCKSEN1 OCKSTH1
R R R
0 PLL1 operation Disable
1 PLL1 operation Enable
0 Output clock is divided clock by setting OCKS11 & OCKS10
1 Output clock is through
OCKS11 OCKS10
0 0
0 1
1 0
1 1
When PLL mode operation is enabled, OCKS1 register value must not be changed.
User's Manual U16702EE3V2UD00
Chapter 6 Clock Generator
4 3 2
0 OCKS11 OCKS10 FFFFF864H
R/W R/W R
Specified for execution enable
Specified for output clock through or divide
Specified for divider factor
f
X
f
X
f
X
f
X
1 0 Address
R/W R/W
/2
/3
/4
/5
After reset
10H
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