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(2)
Low-voltage detection level selection register (LVIS)
The LVIS register is used to select the level of low-voltage to be detected.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Symbol
LVIS
R/W
(3)
Internal RAM data status register (RAMS)
The RAMS register is a flag register that indicates whether the internal RAM is valid or not.
This register can be read or written in 8-bit or 1-bit units
Reset input
Notes: 1. This register can be written only in a specific sequence (see 3.2.3 "Special registers" on
Symbol
RAMS
R/W
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Chapter 24 Low-Voltage Detector
Figure 24-3: Low-Voltage Detection Level Selection Register (LVIS) Format
7
6
5
0
0
0
R
R
R
LVIS0
(4.4 V ±0.2 V)
V
0
LVI0
(4.2 V ±0.2 V)
V
1
LVI1
Note 2
sets this register to 01H.
page 70).
2. Setting conditions: Detection of voltage lower than specified level
Set by instruction
Generation of reset signal by WDT2
Generation of reset signal while RAM is being accessed
Generation of reset signal by clock monitor
Clearing condition: Writing of 0 in specific sequence
Figure 24-4: Internal RAM Data Status Register (RAMS) Format
7
6
5
0
0
0
R
R
R
RAMF
0
valid
1
invalid
User's Manual U16702EE3V2UD00
4
3
2
1
0
0
0
0
R
R
R
R
Detection level
Note 1
.
4
3
2
1
0
0
0
0
R
R
R
R
Internal RAM data valid/invalid
0
Address
After reset
LVIS0
FFFFF891H
00H
R/W
0
Address
After reset
RAMF
FFFFF892H
01H
R/W
783
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