Idle1 Mode; Setting And Operation Status; Releasing Idle1 Mode - NEC V850E/RS1 User Manual

18.4 IDLE1 Mode

18.4.1 Setting and operation status

The IDLE1 mode is set by clearing the PSM1, 0 bit of the power save mode register (PSMR) to 00 and
setting the STP bit of the power save control register (PSC) to 1 in the normal operation mode.
In the IDLE1 mode, the clock oscillator, PLL and Flash continues operation but clock supply to the CPU
and other on-chip peripheral functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE1 mode was
set are retained. Because the IDLE1 stops operation of the on-chip peripheral functions, it reduces the
current consumption to a level lower than the HALT mode.
Table 18-4 shows the operation status in the IDLE1 mode.
The IDLE1 mode can reduce the current consumption more than the HALT mode because it stops the
operation of the on-chip peripheral functions. The main clock oscillator, PLL and Flash does not stop, so
the normal operation mode can be restored without waiting for the oscillation stabilization time after the
IDLE1 mode has been released, in the same manner as when the HALT mode is released.
Caution:

18.4.2 Releasing IDLE1 mode

The IDLE1 mode is released by a non-maskable interrupt request (NMI pin input, INTWDT2
occurrence), unmasked external interrupt request (INTP0 to INTP7 pin input), unmasked internal
interrupt request from the peripheral functions operable in the software IDLE1 mode, or reset signals.
After the IDLE1 mode has been released, the normal operation mode is restored.
(1) Releasing IDLE1 mode by non-maskable interrupt request or unmasked maskable interrupt
request
The IDLE1 mode is released by a non-maskable interrupt request or an unmasked maskable
interrupt request, regardless of the priority of the interrupt request. If the IDLE1 mode is set in an
interrupt servicing routine, however, an interrupt request that is issued later is processed as
follows.
Caution:
(a) If an interrupt request with a priority lower than that of the interrupt request currently being
(b) If an interrupt request with a priority higher than that of the interrupt request currently being
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Chapter 18 Standby Function
Insert five or more NOP instructions after the instruction that stores data in the PSC
register to set the IDLE1 mode.
An interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI1M,
and PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not released.
serviced is issued, only the IDLE1 mode is released, and that interrupt request is not
acknowledged. The interrupt request itself is retained.
serviced is issued (including a non-maskable interrupt request), the IDLE1 mode is released
and that interrupt request is acknowledged.
User's Manual U16702EE3V2UD00 729