Operation; Interval Timer Mode; Clock Generator And Clock Enable Timing - NEC V850E/RS1 User Manual

9.4 Operation

9.4.1 Interval timer mode

In the interval timer mode, a match interrupt signal (INTTM0EQ0) is output when the value of the 16-bit
counter matches the value of TMM0 compare register 0 (TM0CMP0). At the same time, the counter is
cleared to 0000H and starts counting up.
When FFFFH is set to the TM0CMP0 register, timer M performs an operation similar to that in the
free-running mode.
Caution:

9.4.2 Clock generator and clock enable timing

Because the second clock is the first pulse of the timer count-up signal when the TM0CE bit is changed
from 0 to 1, the timer counts one clock less.
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Chapter 9 16-Bit Interval Timer M
Figure 9-4: Interval Timer Mode Timing
Count clock
16-bit counter
TM0CMP0
INTTM0EQ0
To set the interval time to M clocks, set M - 1 to the TM0CMP0 register.
Figure 9-5: Count Operation Start Timing
Clock for counting
TM0CE bit
Clock enable signal
(internal signal)
Count clock
User's Manual U16702EE3V2UD00
M – 2 M – 1 M 0000H
M
0001H