NEC V850E/RS1 User Manual page 738

(2) Power save mode register (PSMR)
This is an 8-bit register that controls the operation status in the power save mode and the clock
operation.
This register can be read or written in 8-bit or 1-bit units.
Symbol
PSMR
R/W
Cautions: 1. Be sure to clear bits 2 to 7 of the PSMR register to 0.
Remark:
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Chapter 18 Standby Function
Figure 18-8: Power Save Mode Register (PSMR) Format
7 6 5
0 0 0
R R R
PSM1 PSM0
(this bit becomes valid when bit 1 (STP) of the PSC register is set to 1)
0 0
0 1
1 0
1 1
2. The PSM0 and PSM1 bits are valid only when the STP bit of the PSC register is 1.
IDLE1: In this mode, all operations except the oscillator operation, flash memory, and PLL
are stopped. After the IDLE1 mode is released, the normal mode need not wait
the lapse of the oscillation stabilization time.
IDLE2: <Case of PLL not use>
In this mode, all operations except the oscillator operation are stopped.
After the IDLE2 mode is released, the normal mode is returned to following the
lapse of the setup time (flash memory) specified by the OSTS register.
<Case of PLL use>
Refer to CHAPTER 6.6.2 How to Use.
STOP: In this mode, all operations are stopped.
After the STOP mode is released, the normal mode is returned to following the
lapse of the oscillation stabilization time specified by the OSTS register.
User's Manual U16702EE3V2UD00
4 3 2 1
0 0 0 PSM1
R R R R/W
Specifies operation in software standby mode
IDLE1 mode
STOP mode
IDLE2 mode
Setting prohibited
0 Address After reset
PSM0 FFFFF820H 00H
R/W