NEC V850E/RS1 User Manual page 230

Note: WR0 and WR1 output a low level as shown in the above timing chart when target data access is
Remarks: 1. The circle indicates the sampling timing when 0 is set for the programmable wait.
230
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Chapter 5 Bus Control Function
Figure 5-13: Address Wait Timing (Bus Size: 16 bit)
T1
T2
CLKOUT
A1
AD15-AD0
ASTB
CSn
WAIT
WR1-WR0
performed. At all other times, these pins output a high level.
2. The broken line indicates high impedance.
TASW T1
D1 Address
00
User's Manual U16702EE3V2UD00
T2 T3
TAHW
Data
00